Enabling access to semiconductor manufacturing is essential to driving innovation, accelerating education, and shaping the future of microelectronics. That’s why we’re excited to announce a new opportunity to bring your chip designs to life: Cadence is offering a multi-project wafer (MPW) aggregation service for designs built on the SKY130 open-source process.
This initiative represents a continued commitment to support the next generation of chip designers, from students and researchers to entrepreneurs and early-stage teams, with an accessible, affordable path to silicon.
A Commitment to Accessible Innovation
Cadence and SkyWater are aligning proven manufacturing processes and advanced verification tools to streamline the journey from concept to fabricated silicon. The MPW aggregation service brings industry-grade tools and open-access process technology to a broader design community, opening new doors for innovation in areas ranging from education to prototyping to IP experimentation.
What the Program Offers
Cadence has designed its MPW service to be simple, cost-effective, and aligned with real-world design constraints. Here’s what designers can expect:
Submission Requirements:
- Designs must be DRC-clean using the Cadence® Pegasus™ Physical Verification Solution, based on the SKY130 design rules.
- OASIS layouts must fit within a 3.588mm x 5.188mm bounding box (a seal ring will be added).
Each submission must be accompanied by:
- An executed legal agreement:
- Payment of USD $10,000 per design
- A valid OASIS file
Deliverables:
- Each accepted participant will receive 40 bare die. Designers are responsible for bring-up, testing, and any packaging or post-silicon validation activities.
MPW Run Schedule: What to Expect
The first opportunity to participate in Cadence’s new MPW aggregation service is quickly approaching, with the inaugural run scheduled for the end of May 2025.
If you’re not ready to submit for this round, don’t worry. This is just the beginning. Cadence plans to offer multiple MPW runs per year, giving designers recurring opportunities to access silicon through the SKY130 platform.
Timeframe for the First Run:
- Finalized DRC rules published: May 2, 2025
- Submission Deadline: Mid-May 2025
- Expected Die Delivery: September 2025 (for U.S.-based participants, subject to SkyWater’s fabrication timeline)
Looking ahead, we anticipate these MPW runs will follow a regular schedule. Future iterations of the program may also introduce options for a standardized package, aligned with a standardized pad ring, based on input from the design community. This will help streamline downstream integration and expand usability.
We’ll continue to share updates as new runs are scheduled—both here and via our social channels—so stay connected and informed.
Supporting the Open Silicon Ecosystem
This program builds on SkyWater’s leadership in open-access foundry services and Cadence’s deep expertise in design enablement and verification workflows. Through this initiative, we hope to make silicon fabrication more inclusive, agile, and responsive to the evolving needs of academic institutions, research labs, startups, and the broader design community.
Our goal is to support this vibrant ecosystem with solutions that are not only accessible and cost-effective but also sustainable for long-term innovation. Whether you’re an educator, a student, or an early-stage innovator, this program is designed to help bring your ideas to life in silicon.
Are You Ready to Get Started?
Contact: Steven Burack
sburack@cadence.com
skywater130mpw@cadence.com
The SKY130 open-source PDK is accessible at https://github.com/google/skywater-pdk.