Integration and packaging as enablers of sustainable quantum scale
By Bassel Haddad
SVP and GM, Foundry Solutions & Technology Platforms, SkyWater Technology
Bassel Haddad leads SkyWater’s Foundry, Advanced Technology Services (ATS), and Technology Platforms business unit. In this role, he is responsible for driving long-term strategic growth, leading go-to-market initiatives, and cultivating strong relationships with customers and partners. He brings more than 25 years of experience in the semiconductor industry including senior business and engineering leadership roles at Intel and Zoran (acquired by Qualcomm), as well as leadership positions at several semiconductor startups.
Quantum hardware spans multiple modalities including superconducting, spin, photonic, trapped ion, and neutral atom systems. Each is built on distinct device physics and brings its own engineering challenges. But despite those differences, they share a critical reality: quantum scaling will not be won by lithographic shrink.
Unlike classical computing, where transistor shrink fueled decades of performance gains, most qubit architectures derive limited benefit from ever-smaller nanometer nodes. Feature size is rarely the primary constraint. Instead, scale is shaped by materials quality, routing density, integration discipline, and system stability.
That reality frames how we should think about scaling.
Qubit count alone does not define scalability. A quantum computer is a layered system composed of:
- The qubit layer, where coherence and gate fidelity originate
- The interconnect layer, which couples qubits and routes signals between them
- The control layer, electronic or optical systems that manipulate and read out qubits
- The infrastructure layer, which keeps the system running and stable
By infrastructure, we mean the engineered systems that enable quantum operation at scale — cryogenic platforms, vacuum systems, thermal management, shielding, and power delivery.
Across these layers sits a critical enabler: manufacturability.
Manufacturability is not a separate layer. It is the multiplier across them. As systems grow, variability compounds. Small deviations in materials, routing, or alignment increase calibration burden, stress system margins, and reduce the number of usable qubits.
At small scale, performance is defined by the qubit layer. As systems grow, the pressure shifts upward into interconnect, control, and infrastructure layers.
Routing density begins to constrain architecture, first within a single die, as qubit counts increase and coupling structures multiply. Eventually, scaling pressure moves beyond a single die, requiring multi-die tiling and 2.5D/3D integration. At that stage, chip-to-chip interconnect density, interposer architecture, and packaging alignment become defining constraints.
Control overhead rises with routing complexity – more signal lines, more control electronics, and more calibration routines to manage. In parallel, thermal load and stability margins at the infrastructure layer begin to set hard scaling limits.
Why 200 mm Wafer Processing Enables Quantum Progress
The industry’s progress over the past decade did not occur in leading-edge transistor fabs. Early development often occurred in vertically integrated environments operating at 150mm wafer sizes across industry, academia and national research labs.
As architectures matured, many platforms began to migrate to 200 mm infrastructure, not to chase smaller features, but because it offered a practical sweet spot for process control, uniformity and scaling manufacturing.
200 mm platforms offer a practical balance of scale, process control and industry maturity and allow:
- An established and widely supported tooling ecosystem
- Greater process stability and enhanced statistical control
- Lower capital intensity relative to advanced 300 mm nodes
- Flexibility to accommodate non-standard materials and custom process flows
For cryogenic circuits in particular, advanced transistor shrink offers limited benefit. Cryogenic control and readout circuits tend to prioritize:
- Strong analog and RF performance
- Stable, predictable device behavior at cryogenic temperatures
- Moderate power density rather than maximum transistor density
- Integration flexibility over extreme scaling
200mm manufacturing provides an environment that balances discipline with flexibility. It lowers barrier to entry, enables faster iteration cycles, and focuses on adaptable but controlled fabrication, while balancing capital efficiency during architectural uncertainty.
200 mm is becoming the foundation on which much of today’s quantum device maturity is built.
Where We Stand Today
Quantum hardware is entering a new phase, not because physics challenges are completely solved, but because scaling considerations now need to move forward in parallel with continued device refinement.
Materials quality, coherence times, and device reproducibility continue to improve. At the same time, system sizes are increasing, and scaling architectures are being defined alongside ongoing advances in qubit physics.
The focus is expanding from improving individual devices in isolation to ensuring those improvements carry through and compound at larger system scale.
Let’s Map That to Two Quantum Modalities: Superconducting and Trapped Ions
Superconducting systems continue to advance in Junction reproducibility, materials refinement, coherence improvements and calibration methods.
These gains remain foundational.
As qubit counts increase, engineering will need to progress in parallel in domains such as intra-die microwave routing density, cryogenic wiring scalability, crosstalk mitigation and control electronics integration.
Beyond single-die scaling, modular multi-die architectures increasingly rely on interposers, TSVs, and advanced packaging. Integration discipline becomes central to sustaining performance as systems grow. Physics refinement and integration scaling are now concurrent efforts.
As interconnect complexity grows, maintaining superconductivity and preserving materials and junction stability with minimal thermal load becomes a key challenge.
Trapped ion platforms continue to demonstrate high-fidelity gates, reproducible microfabricated surface traps, and steady improvements in precise and scalable optical addressing.
Device-level refinement continues. But as systems scale, progress must also extend to optical routing density, surface stability, and vacuum system scalability. As with superconducting systems, scaling increasingly moves from single-device improvement to modular integration, where packaging, optical alignment, and reproducibility determine overall system performance.
Scaling Forward Without Disruption
The key question is straightforward: How do we scale quantum systems while preserving the gains already achieved?
Three principles define the least disruptive path forward.
1. Refine the Physics Engine
Materials stacks, junction processes, trap surfaces, and routing geometries represent years of refinement.
Those gains are cumulative. They should not be destabilized by unnecessary architectural resets or premature process migrations. Scaling must build on the foundation already established.
2. Advance Integration in Parallel
Routing density within individual dies and integration across multi-die assemblies must evolve alongside continued physics refinement.
Scaling architecture should relieve pressure on the interconnect and control layers without disrupting stabilized front-end processes unless there’s a clear and compelling reason to do so.
3. Disciplined Manufacturability
Scaling architecture must preserve process discipline and yield learning. As integration advances, manufacturability should get stronger so performance gains translate into usable system scale.
There is also an economic dimension to this shift. In many quantum platforms, true economies of scale are likely to emerge first at the integration and packaging layers. Wafer-scale packaging, standardized interconnect architectures, and multi-die integration can drive cost improvements without forcing premature changes to stabilized front-end physics.
As device architectures mature, scaling through integration provides a path to economic leverage while preserving hard-won performance gains at the qubit layer. In that sense, manufacturability and integration discipline become not just technical multipliers, but economic ones as well.
Summary
Quantum hardware has made meaningful progress, in materials control and stability, device reproducibility, architectural experimentation, and fabrication discipline. That progress represents years of accumulated learning.
The next phase of scaling must build on that foundation, not reset it.
Physics refinement will continue alongside deliberate advancements in integration architecture. As systems grow, inter-die scaling through 2.5D and 3D packaging is emerging as a critical scale enabler, while providing a path to economic leverage.
At the same time, manufacturability must stabilize and multiply gains across the system stack. It is the discipline that ensures improvements in devices and integration translate into durable, repeatable scale.